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ltc4444 1 4444fb typical application features applications description high voltage synchronous n-channel mosfet driver the ltc ? 4444 is a high frequency high voltage gate driver that drives two n-channel mosfets in a synchronous dc/dc converter with supply voltages up to 100v. this powerful driver reduces switching losses in mosfets with high gate capacitance. the ltc4444 is configured for two supply-independent inputs. the high side input logic signal is internally level-shifted to the bootstrapped supply, which may function at up to 114v above ground. the ltc4444 contains undervoltage lockout circuits that disable the external mosfets when activated. adaptive shoot-through protection prevents both mosfets from conducting simultaneously. for a similar driver in this product family, please refer to the chart below. parameter ltc4444 ltc4446 ltc4444-5 shoot-through protection yes no yes absolute max ts 100v 100v 100v mosfet gate drive 7.2v to 13.5v 7.2v to 13.5v 4.5v to 13.5v v cc uv + 6.6v 6.6v 4v v cc uv C 6.15v 6.15v 3.55v n bootstrap supply voltage to 114v n wide v cc voltage: 7.2v to 13.5v n adaptive shoot-through protection n 2.5a peak tg pull-up current n 3a peak bg pull-up current n 1.2 tg driver pull-down n 0.55 bg driver pull-down n 5ns tg fall time driving 1nf load n 8ns tg rise time driving 1nf load n 3ns bg fall time driving 1nf load n 6ns bg rise time driving 1nf load n drives both high and low side n-channel mosfets n undervoltage lockout n thermally enhanced 8-pin msop package n distributed power architectures n automotive power supplies n high density power modules n telecommunications high input voltage buck converter ltc4444 driving a 1000pf capacitive load l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6677210. tg boost v in 100v (abs max) gnd ts v cc tinp ltc4444 bg pwm2 (from controller ic) pwm1 (from controller ic) v cc 7.2v to 13.5v binp v out 4444 ta01a binp 5v/div bg 10v/div tinp 5v/div tg-ts 10v/div 20ns/div 4444 ta01b
ltc4444 2 4444fb pin configuration absolute maximum ratings supply voltage v cc ......................................................... C0.3v to 14v boost C ts ........................................... C0.3v to 14v tinp voltage ..................................................C2v to 14v binp voltage ..................................................C2v to 14v boost voltage .........................................C0.3v to 114v ts voltage .................................................. C5v to 100v operating junction temperature range (notes 2, 3) ........................................ C55c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) ................... 300c (note 1) 1 2 3 4 tinp binp v cc bg 8 7 6 5 ts tg boost nc top view 9 gnd ms8e package 8-lead plastic msop t jmax = 125c, ja = 40c/w, jc = 10c/w (note 4) exposed pad (pin 9) is gnd, must be soldered to pcb order information electrical characteristics symbol parameter conditions min typ max units gate driver supply, v cc v cc operating voltage 7.2 13.5 v i vcc dc supply current tinp = binp = 0v 350 550 a uvlo undervoltage lockout threshold v cc rising v cc falling hysteresis l l 6.00 5.60 6.60 6.15 450 7.20 6.70 v v mv bootstrapped supply (boost C ts) i boost dc supply current tinp = binp = 0v 0.1 2 a input signal (tinp , binp) v ih(bg) bg turn-on input threshold binp ramping high l 2.25 2.75 3.25 v v il(bg) bg turn-off input threshold binp ramping low l 1.85 2.3 2.75 v v ih(tg) tg turn-on input threshold tinp ramping high l 2.25 2.75 3.25 v v il(tg) tg turn-off input threshold tinp ramping low l 1.85 2.3 2.75 v i tinp(binp) input pin bias current 0.01 2 a the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = v boost = 12v, v ts = gnd = 0v, unless otherwise noted. lead free finish tape and reel part marking* package description temperature range ltc4444ems8e#pbf ltc4444ems8e#trpbf ltdbf 8-lead plastic msop C40c to 125c ltc4444ims8e#pbf ltc4444ims8e#trpbf ltdbf 8-lead plastic msop C40c to 125c ltc4444hms8e#pbf ltc4444hms8e#trpbf ltdbf 8-lead plastic msop C40c to 150c ltc4444mpms8e#pbf ltc4444mpms8e#trpbf ltdbf 8-lead plastic msop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a l abel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc4444 3 4444fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4444 is tested under pulsed load conditions such that t j t a . the ltc4444e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, charac- terization and correlation with statistical process controls. the ltc4444i is guaranteed over the C40c to 125c operating temperature range, the ltc4444h is guaranteed over the C40c to 150c operating temperature range and the ltc4444mp is tested and guaranteed over the full C55c to 150c operating junction temperature range. high junction temperatures electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = v boost = 12v, v ts = gnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units high side gate driver output (tg) v oh(tg) tg high output voltage i tg = C10ma, v oh(tg) = v boost C v tg 0.7 v v ol(tg) tg low output voltage i tg = 100ma, v ol(tg) = v tg Cv ts l 120 250 mv i pu(tg) tg peak pull-up current l 1.7 2.5 a r ds(tg) tg pull-down resistance l 1.2 2.5 low side gate driver output (bg) v oh(bg) bg high output voltage i bg = C10ma, v oh(bg) = v cc C v bg 0.7 v v ol(bg) bg low output voltage i bg = 100ma l 55 125 mv i pu(bg) bg peak pull-up current l 23 a r ds(bg) bg pull-down resistance l 0.55 1.25 switching time [binp (tinp) is tied to ground while tinp (binp) is switching. refer to timing diagram] t plh(tg) tg low-high propagation delay l 25 50 ns t phl(tg) tg high-low propagation delay l 22 45 ns t plh(bg) bg low-high propagation delay l 19 40 ns t phl(bg) bg high-low propagation delay l 14 35 ns t r(tg) tg output rise time 10% C 90%, c l = 1nf 10% C 90%, c l = 10nf 8 80 ns ns t f(tg) tg output fall time 10% C 90%, c l = 1nf 10% C 90%, c l = 10nf 5 50 ns ns t r(bg) bg output rise time 10% C 90%, c l = 1nf 10% C 90%, c l = 10nf 6 60 ns ns t f(bg) bg output fall time 10% C 90%, c l = 1nf 10% C 90%, c l = 10nf 3 30 ns ns degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 4: failure to solder the exposed back side of the ms8e package to the pc board will result in a thermal resistance much higher than 40c/w.
ltc4444 4 4444fb typical performance characteristics v cc supply quiescent current vs voltage boost-ts supply quiescent current vs voltage v cc supply current vs temperature boost supply current vs temperature output low voltage (v ol ) vs supply voltage output high voltage (v oh ) vs supply voltage input thresholds (tinp , binp) vs supply voltage input thresholds (tinp , binp) vs temperature input thresholds (tinp , binp) hysteresis vs voltage v cc supply voltage (v) 0 0 quiescent current (a) 50 150 200 250 6 7 8 9 10 11 12 13 450 4444 g01 100 12345 14 300 350 400 tinp = binp = 0v tinp(binp) = 12v t a = 25c boost = 12v ts = gnd boost supply voltage (v) 0 0 quiescent current (a) 50 150 200 250 6 7 8 9 10 11 12 13 400 4444 g02 100 12345 14 300 350 tinp = binp = 0v tinp = 0v, binp = 12v tinp = 12v, binp = 0v t a = 25c v cc = 12v ts = gnd temperature (c) v cc supply current (a) 350 360 370 4444 g03 330 300 C55 C25 5 35 65 95 125 150 380 340 320 310 tinp = binp = 0v v cc = boost = 12v ts = gnd tinp(binp) = 12v temperature (c) boost supply current (a) 250 300 350 4444 g04 150 0 400 200 100 50 tinp = 12v binp = 0v tinp = 0v binp = 12v tinp = binp = 0v v cc = boost = 12v ts = gnd C55 C25 5 35 65 95 125 150 supply voltage (v) 7 output voltage (mv) 140 10 4444 g05 80 40 89 11 20 0 160 120 100 60 12 13 14 v ol(tg) v ol(bg) t a = 25c i tg(bg) = 100ma boost = v cc ts = gnd supply voltage (v) 7 5 tg or bg output voltage (v) 6 8 9 10 15 12 9 11 12 4444 g06 7 13 C1ma 14 11 8 10 13 14 t a = 25c boost = v cc ts = gnd C10ma C100ma supply voltage (v) 7 2.1 tg or bg input threshold (v) 2.2 2.4 2.5 2.6 3.1 2.8 9 11 12 4444 g07 2.3 2.9 3.0 2.7 8 10 13 14 t a = 25c boost = v cc ts = gnd v ih(tg,bg) v il(tg,bg?) supply voltage (v) 78 375 tg or bg input threshold hysteresis (mv) 425 500 9 11 12 4444 g09 400 475 450 10 13 14 t a = 25c v cc = boost = 12v ts = gnd C55 C25 5 35 65 95 125 150 temperature (c) tg or bg input threshold (v) 2.6 2.8 3.0 4444 g08 2.4 2.2 2.5 2.7 2.9 2.3 2.1 2.0 v cc = boost = 12v ts = gnd v ih(tg,bg) v il(tg,bg)
ltc4444 5 4444fb typical performance characteristics input thresholds (tinp , binp) hysteresis vs temperature v cc undervoltage lockout thresholds vs temperature rise and fall time vs v cc supply voltage rise and fall time vs load capacitance peak driver (tg, bg) pull-up current vs temperature output driver pull-down resistance vs temperature propagation delay vs v cc supply voltage propagation delay vs temperature temperature (c) 375 tg or bg input threshold hysteresis (mv) 425 500 4444 g10 400 475 450 v cc = boost = 12v ts = gnd C55 C25 5 35 65 95 125 150 C55 C25 5 35 65 95 125 150 temperature (c) 6.0 v cc suplly voltage (v) 6.1 6.3 6.4 6.5 6.7 4444 g11 6.2 6.6 rising threshold falling threshold boost = v cc ts = gnd supply voltage (v) 7 rise/fall time (ns) 12 28 30 22 26 32 9 11 12 4444 g12 8 20 16 10 24 6 18 14 8 10 13 14 t a = 25c boost = v cc ts = gnd c l = 3.3nf t r(tg) t r(bg) t f(tg) t f(bg) load capacitance (nf) 1 rise/fall time (ns) 40 50 60 9 4444 g13 30 20 0 3 5 7 210 4 6 8 10 80 70 t r(tg) t r(bg) t f(tg) t f(bg) t a = 25c v cc = boost = 12v ts = gnd C55 C25 5 35 65 95 125 150 temperature (c) 2.0 pull-up current (a) 2.2 2.6 2.8 3.0 3.4 4444 g14 2.4 3.2 i pu(bg) i pu(tg) v cc = boost = 12v ts = gnd temperature (c) output driver pull-down resistacne () 1.2 1.6 2.0 2.2 4444 g15 0.8 0.4 1.0 1.4 1.8 0.6 0.2 v cc = 14v v cc = 7v r ds(tg) r ds(bg) boost-ts = 7v C55 C25 5 35 65 95 125 150 boost-ts = 12v v cc = 12v boost-ts = 14v supply voltage (v) 7 10 propagation delay (ns) 12 16 18 20 30 24 9 11 12 4444 g16 14 26 28 22 8 10 13 14 t a = 25c boost = v cc ts = gnd t plh(tg) t plh(bg) t phl(bg) t phl(tg) C55 C25 5 35 65 95 125 150 temperature (c) 2 propagation delay (ns) 7 17 22 27 37 4444 g17 12 32 v cc = boost = 12v ts = gnd t plh(tg) t phl(tg) t plh(bg) t phl(bg)
ltc4444 6 4444fb pin functions typical performance characteristics switching supply current vs input frequency switching supply current vs load capacitance tinp (pin 1): high side input signal. input referenced to gnd. this input controls the high side driver output (tg). binp (pin 2): low side input signal. this input controls the low side driver output (bg). v cc (pin 3): supply. this pin powers input buffers, logic and the low side gate driver output directly and the high side gate driver output through an external diode con- nected between this pin and boost (pin 6). a low esr ceramic bypass capacitor should be tied between this pin and gnd (pin 9). bg (pin 4): low side gate driver output (bottom gate). this pin swings between v cc and gnd. nc (pin 5): no connect. no connection required. boost (pin 6): high side bootstrapped supply. an ex- ternal capacitor should be tied between this pin and ts (pin 8). normally, a bootstrap diode is connected between v cc (pin 3) and this pin. voltage swing at this pin is from v cc C v d to v in + v cc C v d , where v d is the forward volt- age drop of the bootstrap diode. tg (pin 7): high side gate driver output (top gate). this pin swings between ts and boost. ts (pin 8): high side mosfet source connection (top source). gnd (exposed pad pin 9): ground. must be soldered to pcb ground for optimal thermal performance. switching frequency (khz) 0 supply current (ma) 1.5 2.0 2.5 600 1000 4444 g18 1.0 0.5 0 200 400 800 3.0 3.5 4.0 i boost (tg switching) i boost (bg switching) i vcc (bg switching) i vcc (tg switching) t a = 25c v cc = boost = 12v ts = gnd load capacitance (nf) 1 supply current (ma) 10 100 1345 0.1 2789 6 10 4444 g19 i vcc (bg switching at 1mhz) i boost (tg switching at 500khz) i boost (tg switching at 1mhz) i boost (bg switching at 1mhz or 5ookhz) i vcc (bg switching at 500khz) i vcc (tg switching at 500khz) i vcc (tg switching at 1mhz)
ltc4444 7 4444fb block diagram 3 6 7 9 high side level shifter v cc uvlo ldo v int v cc gnd 7.2v to 13.5v boost v in up to 100v tg 8 ts bg 4444 bd 1 tinp binp 2 5 nc low side level shifter antishoot-through protection v cc v cc 4 timing diagrams 90% input rise/fall time < 10ns tinp (binp) bg (tg) binp (tinp) tg (bg) 90% 90% t r t f t phl t plh 10% 4444 td02 10% 10% switching time adaptive shoot-through protection binp bg tinp tg-ts binp bg tinp tg-ts 4444 td01
ltc4444 8 4444fb operation overview the ltc4444 receives ground-referenced, low voltage digi- tal input signals to drive two n-channel power mosfets in a synchronous buck power supply configuration. the gate of the low side mosfet is driven either to v cc or gnd, depending on the state of the input. similarly, the gate of the high side mosfet is driven to either boost or ts by a supply bootstrapped off of the switching node (ts). input stage the ltc4444 employs cmos compatible input thresholds that allow a low voltage digital signal to drive standard power mosfets. the ltc4444 contains an internal voltage regulator that biases both input buffers for high side and low side inputs, allowing the input thresholds (v ih = 2.75v, v il = 2.3v) to be independent of variations in v cc . the 450mv hysteresis between v ih and v il eliminates false triggering due to noise during switching transitions. however, care should be taken to keep both input pins (tinp and binp) from any noise pickup, especially in high frequency, high voltage applications. the ltc4444 input buffers have high input impedance and draw negligible input current, simplifying the drive circuitry required for the inputs. 6 boost ltc4444 8 ts tg 7 v in up to 100v q1 m1 c gs c gd 3 v cc 9 gnd 4 bg q2 m2 low side power mosfet high side power mosfet c gs c gd load inductor 4444 fo1 figure 1. capacitance seen by bg and tg during switching output stage a simplified version of the ltc4444s output stage is shown in figure 1. the pull-up devices on the bg and tg outputs are npn bipolar junction transistors (q1 and q2). the bg and tg outputs are pulled up to within an npn v be (~0.7v) of their positive rails (v cc and boost, respectively). both bg and tg have n-channel mosfet pull-down devices (m1 and m2) which pull bg and tg down to their nega- tive rails, gnd and ts. the large voltage swing of the bg and tg output pins is important in driving external power mosfets, whose r ds(on) is inversely proportional to the gate overdrive voltage (v gs ? v th ). rise/fall time the ltc4444s rise and fall times are determined by the peak current capabilities of q1 and m1. the predriver that drives q1 and m1 uses a nonoverlapping transition scheme to minimize cross-conduction currents. m1 is fully turned off before q1 is turned on and vice versa. since the power mosfet generally accounts for the ma- jority of the power loss in a converter, it is important to quickly turn it on or off, thereby minimizing the transition time in its linear region. an additional benefit of a strong
ltc4444 9 4444fb pull-down on the driver outputs is the prevention of cross- conduction current. for example, when bg turns the low side (synchronous) power mosfet off and tg turns the high side power mosfet on, the voltage on the ts pin will rise to v in very rapidly. this high frequency positive voltage transient will couple through the c gd capacitance of the low side power mosfet to the bg pin. if there is an insufficient pull-down on the bg pin, the voltage on the bg pin can rise above the threshold voltage of the low side power mosfet, momentarily turning it back on. with both the high side and low side mosfets conducting, significant cross-conduction current will flow through the mosfets from v in to ground and will cause substantial power loss. a similar effect occurs on tg due to the c gs and c gd capacitances of the high side mosfet. the powerful output driver of the ltc4444 reduces the switching losses of the power mosfet, which increase with transition time. the ltc4444s high side driver is capable of driving a 1nf load with 8ns rise and 5ns fall times using a bootstrapped supply voltage v boost-ts of 12v while its low side driver is capable of driving a 1nf load with 6ns rise and 3ns fall times using a supply volt- age v cc of 12v. undervoltage lockout (uvlo) the ltc4444 contains an undervoltage lockout detector that monitors v cc supply. when v cc falls below 6.15v, the output pins bg and tg are pulled down to gnd and ts, respectively. this turns off both external mosfets. when v cc has adequate supply voltage, normal operation will resume. adaptive shoot-through protection internal adaptive shoot-through protection circuitry moni- tors the voltages on the external mosfets to ensure that they do not conduct simultaneously. this feature improves efficiency by eliminating cross-conduction current from flowing from the v in supply through both of the mosfets to ground during a switch transition. if both tinp and binp are high at the same time, bg will be kept off and tg will be turned on (refer to the timing diagram). if bg is still high when tinp turns on, tg will not be turned on until bg goes low. when tinp turns off, the adaptive shoot-through protec- tion circuitry monitors the level of the ts pin. bg can be turned on if the ts pin goes low. if the ts pin stays high, bg will be turned on 150ns after tinp turns off. applications information power dissipation to ensure proper operation and long-term reliability, the ltc4444 must not operate beyond its maximum tem- perature rating. package junction temperature can be calculated by: t j = t a + p d ( ja ) where: t j = junction temperature t a = ambient temperature p d = power dissipation ja = junction-to-ambient thermal resistance power dissipation consists of standby and switching power losses: p d = p dc + p ac + p qg where: p dc = quiescent power loss p ac = internal switching loss at input frequency, f in p qg = loss due turning on and off the external mosfet with gate charge qg at frequency f in the ltc4444 consumes very little quiescent current. the dc power loss at v cc = 12v and v boost-ts = 12v is only (350a)(12v) = 4.2mw. operation
ltc4444 10 4444fb applications information at a particular switching frequency, the internal power loss increases due to both ac currents required to charge and discharge internal node capacitances and cross-conduc- tion currents in the internal logic gates. the sum of the quiescent current and internal switching current with no load are shown in the typical performance characteristics plot of switching supply current vs input frequency. the gate charge losses are primarily due to the large ac currents required to charge and discharge the capacitance of the external mosfets during switching. for identical pure capacitive loads c load on tg and bg at switching frequency f in , the load losses would be: p cload = (c load )(f)[(v boost-ts ) 2 + (v cc ) 2 ] in a typical synchronous buck configuration, v boost-ts is equal to v cc C v d , where v d is the forward voltage drop across the diode between v cc and boost. if this drop is small relative to v cc , the load losses can be approximated as: p cload = 2(c load )(f in )(v cc ) 2 unlike a pure capacitive load, a power mosfets gate capacitance seen by the driver output varies with its v gs voltage level during switching. a mosfets capacitive load power dissipation can be calculated using its gate charge, qg. the qg value corresponding to the mosfets v gs value (v cc in this case) can be readily obtained from the manufacturers qg vs v gs curves. for identical mosfets on tg and bg: p qg = 2(v cc )(q g )(f in ) to avoid damage due to power dissipation, the ltc4444 includes a temperature monitor that will pull bg and tg low if the junction temperature rises above 160c. normal operation will resume when the junction temperature cools to less than 135c. bypassing and grounding the ltc4444 requires proper bypassing on the v cc and v boost-ts supplies due to its high speed switching (nanoseconds) and large ac currents (amperes). careless component placement and pcb trace routing may cause excessive ringing. to obtain the optimum performance from the ltc4444: a. mount the bypass capacitors as close as possible between the v cc and gnd pins and the boost and ts pins. the leads should be shortened as much as possible to reduce lead inductance. b. use a low inductance, low impedance ground plane to reduce any ground drop and stray capacitance. remember that the ltc4444 switches greater than 3a peak currents and any significant ground drop will degrade signal integrity. c. plan the power/ground routing carefully. know where the large load switching current is coming from and going to. maintain separate ground return paths for the input pin and the output power stage. d. keep the copper trace between the driver output pin and the load short and wide. e. be sure to solder the exposed pad on the back side of the ltc4444 package to the board. correctly soldered to a 2500mm 2 double sided 1oz copper board, the ltc4444 has a thermal resistance of approximately 40c/w for the ms8e package. failure to make good thermal contact between the exposed back side and the copper board will result in thermal resistances far greater than 40c/w.
ltc4444 11 4444fb pgood ss sense + sense C i th v osense sgnd run fcb pllfltr pllin stbymd boost1 tg1 sw1 v in extv cc intv cc bg1 pgnd bg2 sw2 tg2 boost2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ltc3780eg 10k 100 100 220k v os + 15k 220k 487k 1% 8.25k 1% 1000pf 100pf 47pf v in d5 0.1f 100v 68pf 0.022f 0.1f 16v 2.2f, 100v, tdk c4532x7r2a225mt c1: sanyo 100me100hc +t c2, c3: sanyo 63me220hc + t d1: on semi mmdl770t1g d2: diodes inc. 1n5819hw-7-f d3, d4: diodes inc. pds560-13 d5: diodes inc. mmbz5230b-7-f d6: diodes inc. b1100-13-f l1: sumida cdep147np-100mc-125 r1, r2: vishay dale wsl2512r0250fea 0.1f 16v 6v 10f 10v 6v 1f 16v 0.22f 16v l1 10h 2.2f 100v s 4 c1 100f 100v v in 1f 16v 0.1f 16v v bias 10v to 12v v bias 10v to 12v d1 sense + sense C 6v d2 1 2 4 6 7 8 9 3 v cc gnd tg boost tinp binp ltc4444 ts bg + 2.2f 100v s 8 c2,c3 220f 63v s 2 v out + r1 0.025 1w 4444 ta02a d6 sense + sense C d3 d4 r2 0.025 1w 10 10 v os + 10 typical application ltc3780 high efficiency 36v to 72v v in to 48v/6a buck-boost dc/dc converter load current (a) 95 efficiency (%) 96 97 98 2 1345 4444 ta02b 6 v in = 36v v in = 48v v in = 72v efficiency
ltc4444 12 4444fb package description msop (ms8e) 0910 rev i 0.53 t 0.152 (.021 t .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 s C 6 s typ detail a detail a gauge plane 12 3 4 4.90 t 0.152 (.193 t .006) 8 8 1 bottom view of exposed pad option 7 6 5 3.00 t 0.102 (.118 t .004) (note 3) 3.00 t 0.102 (.118 t .004) (note 4) 0.52 (.0205) ref 1.68 (.066) 1.88 (.074) 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 1.68 t 0.102 (.066 t .004) 1.88 t 0.102 (.074 t .004) 0.889 t 0.127 (.035 t .005) recommended solder pad layout 0.65 (.0256) bsc 0.42 t 0.038 (.0165 t .0015) typ 0.1016 t 0.0508 (.004 t .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref ms8e package 8-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1662 rev i)
ltc4444 13 4444fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 06/10 mp-grade part added. reflected throughout the data sheet. 1 to 14 b 01/11 h-grade part added. reflected throughout the data sheet. 1 to 14
ltc4444 14 4444fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0111 rev b ? printed in usa related parts typical application ltc3780 high efficiency 8v to 80v v in to 12v/5a buck-boost dc/dc converter part number description comments ltc4446 high voltage synchronous n-channel mosfet driver without shoot-through protection up to 100v supply voltage, 7.2v v cc 13.5v, 3a peak pull-up/ 0.55 peak pull-down ltc4440/ltc4440-5 high speed, high voltage, high side gate driver up to 80v supply voltage, 8v v cc 15v, 2.4a peak pull-up/ 1.5 peak pull-down ltc4442 high speed synchronous n-channel mosfet driver up to 38v supply voltage, 6v v cc 9.5v, 3.2a peak pull-up/ 4.5a peak pull-down ltc4449 high speed synchronous n-channel mosfet driver up to 38v supply voltage, 4.5v v cc 6.5v, 3.2a peak pull-up/ 4.5a peak pull-down ltc4441/ltc4441-1 n-channel mosfet gate driver up to 25v supply voltage, 5v v cc 25v, 6a peak output current ltc1154 high side micropower mosfet driver up to 18v supply voltage, 85a quiescent current, h-grade available pgood ss sense + sense C i th v osense sgnd run fcb pllfltr pllin stbymd boost1 tg1 sw1 v in extv cc intv cc bg1 pgnd bg2 sw2 tg2 boost2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ltc3780eg 10k 100 20k 100 v os + 150k 113k 1% 8.06k 1% 0.01f 47pf v in d4 0.1f 100pf 68pf 0.1f 0.1f 2.2f, 100v, tdk c4532x7r2a225mt 100f, 100v sanyo 100me 100ax c1: sanyo 16me330wf d1: diodes inc. bav19ws d2: diodes inc. 1n5819hw-7-f d3: diodes inc. b320a-13-f d4: diodes inc. mmbz5230b-7-f d5: diodes inc. b1100-13-f l1: sumida cdep147-8r0 0.1f 16v 6v 10f 10v tg1 sw1 1f 16v 0.22f 16v 0.22f 16v l1 8h 2.2f 100v s 5 100f 100v s 2 v in 8v to 80v 1f 16v 0.1f 16v v bias 12v v bias 12v d1 sense + sense C 6v d2 6v 1 2 4 tg1 6 7 8 9 3 v cc gnd tg boost tinp binp ltc4444 ts bg + 22f 16v s 3 c1 330f s 2 v out 12v, 5a 10 v os + + 4444 ta03 d5 sense + sense C d3 sw1 0.005 1w 10 10

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